Portable electronic devices such as radiotelephones continue to grow in popularity. Makers of such devices continue to improve the speed, functionality and battery life of these devices utilizing computer aided design tools such as Physical Compiler from Synopsys or First Encounter by Cadence Inc. These tools can operate on mainframes that utilize workstations or on personal computers possibly internetworking with other computers.
Many portable electronic products or devices have functional systems on a single microchip or integrated circuit (IC). This configuration is often referred to as a “system on a chip” (SoC). A SoC can have a clock tree or clock system that provides clock signals to design elements, referred to herein as “cells,” that are selected from a cell library. The clock tree provides clock signals throughout the IC such that multiple circuits on the IC can be time synchronized. Such clock trees can become large and consume a significant portion of the total power required to operate the IC due in part to poor clock system design. Typically, the clock system is one of the last circuits configured or “placed” during the design process. This occurs because until all synchronous cells are in place, the designer or CAD (computer aided design) tool does not know where to place clock drivers. As a result, clock tree components are often patched into the design late in the design process utilizing left over space. Such a design progression requires some branches or conductors within the clock tree to be relatively long, and synchronous cells that terminate the conductors are often located in less than desirable locations with less than desirable interconnect configurations relative the clock tree. Accordingly, there is a need for systems and methods to improve clock systems in integrated circuits.